1. Field of the Invention
The present invention relates to integrated circuit technology wherein it is desirable to provide an output pulse having rising and falling edges that are independently delayed by predetermined different amounts from the rising and falling edges of an input pulse. More particularly, the invention concerns an improved, low cost CMOS circuit for providing such a function.
2. Discussion of Related Art
Various transistor circuits exist in the prior art that are capable of programmable pulse generation. For example, U.S. Pat. No. 3,906,247 describes a programmable proportional clock edge delay circuit. The patented circuit provides independent control over the rising and falling edges of an output circuit by means of a voltage comparator that requires ramp generator control means to initiate successive clock pulses for alternately initiating and terminating the ramp voltage generation. It is not clear, however, how such a circuit could be implemented in CMOS technology; nor is the circuit of the same speed and operational efficiency as Applicants' claimed invention.
U.S. Pat. No. 4,580,065 describes an integrated circuit single shot generator for providing a desired duty cycle. However, the circuit does not disclose a technique for establishing independent control of rising and falling edges of an input signal.
U.S. Pat. No. 4,675,546 discloses an edge programmable timing signal generator which is completely implemented in digital logic configuration. However, the circuitry involved is much more complicated than that described in Applicants' specification.